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诸葛晴凤

教授,博士生导师大数据智能系统团队负责人

计算机科学与技术学院      

个人资料

  • 部门: 计算机科学与技术学院
  • 毕业院校: 复旦大学,美国德克萨斯大学达拉斯分校
  • 学位: 博士
  • 学历:
  • 邮编:
  • 联系电话: 021-62233333
  • 传真:
  • 电子邮箱: qfzhuge@cs.ecnu.edu.cn
  • 办公地址: 华东师范大学 中山北路校区 理科大楼B-613
  • 通讯地址:

教育经历

University of Texas at Dallas, PHD in Computer Science

复旦大学,硕士、学士


请注意:国际知名学者 沙行勉教授 诚征大数据智能系统方向的研究生!沙行勉老师的信息如下:


沙行勉老师,国际知名学者,华东师范大学终身特聘教授,大数据智能系统方向领军人。沙老师在多核并行和分布式系统、操作系统、大数据处理系统及网络、先进存储、调度与资源分配、算法设计等领域处于国际领先水平,获得多项国际学术奖项,和产业界保持长期深度合作关系。诚挚欢迎有志在计算机系统方向发展的保研和考研学生主动联系沙老师。

沙老师邮箱:edwinsha@cs.ecnu.edu.cn,欢迎提前联系!


由于沙行勉老师的信息受到一定程度的保护,暂时不便完全公开,需要了解更多沙行勉老师信息请访问团队网页,大数据智能系统团队其他成员的详细介绍也请在实验室网页查看。

欢迎关注大数据智能系统团队实验室 https://bdislab.github.io/index.html


工作经历

个人简介

    诸葛晴凤教授,紫江学者,博士生导师1992年本科毕业于复旦大学电子工程系;1996年获复旦大学硕士学位;后于2001年和2003年分别获美国德克萨斯大学达拉斯分校 (University of Texas at Dallas, UTD) 计算机科学硕士学位博士学位,获最佳博士论文奖(Best Dissertation Award)。曾任Unisys公司高级信息顾问;Evavi公司科学家、资深系统架构师在学术界和工业界专业领域都有多年的从业经历,长期和海内外多所知名高校以及专家学者保持密切的国际学术合作与交流

    诸葛教授在高性能并行与分布式系统、调度与资源分配,先进存储结构的数据分布,算法设计与优化,软硬件协同设计与优化,人工智能加速器设计与优化,以及相关的应用领域,例如智慧教育,智能物流等领域做了大量的研究工作,很多成果处于国际前沿领先水平,在国际重要学术会议及国际核心期刊上发表学术论文180多篇,其中包括70多篇的国际期刊论文(IEEE Transactions,ACM Transactions或其他SCI期刊等),多次在国际学术会议获得最佳论文奖或最佳论文提名,论文他引次数近2000多次,多篇论文被国际知名学者引用,研究成果已申请技术发明专利30多项,其中,国际或国利8项。她的研究获得多个国家级、省部级、工业界研究项目的支持,是国家科技部863项目负责人、自然科学基金项目负责人。

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诸葛晴凤教授正在招收博士生硕士生(学硕和专硕),欢迎有志向的学生报考,在活泼开放的氛围中,在老师的亲自指导之下,和国际化团队合作,提升实际动手能力,从事前沿的科学探索和研究,和实验室的师兄师姐们共同学习,一起进步。

请在“计算机科学系”报名网页登录你的信息,学科方向:计算机科学。

  

诸葛教授邮箱:qfzhuge@cs.ecnu.edu.cn ,欢迎提前联系。

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社会兼职

电气电子工程师协会IEEE会员

国际计算机学会ACM会员

中国计算机学会CCF会员

 

研究方向

并行与分布式计算,存内计算(In-Memory Computing),

面向智能计算的系统软件与存储优化,智能化数据存储与数据管理,

资源分配与调度,算法与应用的设计与分析,嵌入式系统,软/硬件协同设计等。


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诸葛晴凤教授正在招收博士生硕士生(学硕和专硕),欢迎有志向的学生报考,在活泼开放的氛围中,在老师的亲自指导之下,和国际化团队合作,提升实际动手能力,从事前沿的科学探索和研究,和实验室的师兄师姐们共同学习,一起进步。

请在“计算机科学系”报名网页登录你的信息,学科方向:计算机科学。

诸葛教授邮箱:qfzhuge@cs.ecnu.edu.cn ,欢迎提前联系。

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诸葛晴凤教授目前担任大数据智能系统团队负责人。

请注意大数据智能系统实验室的沙行勉老师也在诚征研究生,他的信息如下:


沙行勉老师,华东师范大学终身特聘教授,大数据智能系统方向领军人,特聘专家学者。沙老师在多核并行和分布式系统、操作系统、软硬件协同设计、大数据系统及网络、嵌入式系统、优化算法设计等方面做世界一流的研究。同时,沙老师是多个国家级科研项目的主持人,和产业界有长期深度合作关系。诚挚欢迎保研和考研学生前来申请成为沙行勉老师的学生!

沙教授邮箱:edwinsha@cs.ecnu.edu.cn,欢迎提前联系!



开授课程

科研项目

部分研究项目

1.科技部国家高技术研究发展计划(863计划)项目负责人,“面向大数据应用的新型内存计算系统软件及关键技术”

2.中国国家自然科学基金(NSFC)面上项目,项目负责人,“面向高性能嵌入式系统的软件并行化和数据分布优化”

3.科技部国家高技术研究发展计划(863计划),“基于新型非易失性存储器的‘统一内外存’系统结构及其关键技术”

4.上海市科委人工智能教育专项子课题,“基于学生成长大数据的成长监测系统与教育人工智能大脑关键技术研究

5.企业合作项目“基于新型存储介质的文件系统架构及核心算法研究”,“SCM+NVM Flash混合存储软件栈关键技术及算法研究”,“基于SCM NVM介质和系统的关键技术研究”,“面向持久化内存及分布式架构的低开销用户态文件系统软件研究”等


学术成果

 近年发表的部分论文成果:

(Referred Journal Publications)

1.       “BOSS: An Efficient Data Distribution Strategy for Object Storage Systems with Hybrid Devices”. In IEEE Access, vol. 5, pp. 23979-23993, Sept. 2017. (SCI Indexed, JCR Q1)

2.      Refinery Swap: An Efficient Swap Mechanism for Hybrid DRAM-NVM Systems”. Future Generation Computer Systems (FGCS), 2017, 77:52-64. (SCI Indexed, JCR Q1)

3.       "Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory," in IEEE Transactions on Computers (TC), vol. 67, no. 3, pp. 432-448, Mar. 2018. (SCI Indexed, JCR Q1)

4.       "Synthesizing Distributed Pipelining Systems with Timing Constraints via Optimal Functional Unit Assignment and Communication Selection," Journal of Computational Science (JOCS), 2017. (SCI Indexed)

5.       "Optimal Functional-Unit Assignment for Heterogeneous Systems under Timing Constraint," IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume: 28, Issue: 9, 2017. (SCI Indexed, JCR Q1)

6.       "Efficient Assignment Algorithms to Minimize Operation Cost for Supply Chain Networks in Agile Manufacturing," in Computers & Industrial Engineering (CAIE), Volume: 108, 2017. (SCI Indexed, JCR Q2)

7.       基于非易失性内存的持久化嵌入式内存数据库. 软件学报, 2016, 27(S2):320-327.

8.       A Unified Framework for Designing High Performance In-memory and Hybrid Memory File Systems”. Journal of Systems Architecture (JSA), vol. 68, pp. 51-64 Aug. 2016. (SCI Indexed, JCR Q2)

9.       A New Design of In-Memory File System Based on File Virtual Address Framework,” in IEEE Transactions on Computers (IEEE TC), Vol. 65, No. 10, pp. 2959-2972, Oct. 2016, Received the Honor of Editor’s Pick of the Year of 2016. (SCI Indexed, JCR Q1)

10.    “Synthesizing Distributed Pipelining Systems with Timing Constraints via Optimal Functional Unit Assignment and Communication Selection,” in Journal of Computational Science, Mar. 2017. (SCI Indexed)

11.    “Optimal Functional-Unit Assignment for Heterogeneous Systems under Timing Constraint,” in IEEE Transactions on Parallel and Distributed Systems, Mar. 2017. DOI:10.1109/TPDS.2017.2676764. (SCI Indexed, JCR Q1)

12.    “FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era,” in IEEE Transactions on Parallel and Distributed Systems, Dec. 2016. DOI:10.1109/TPDS.2016.2643669. (SCI Indexed, JCR Q1)

13.    “Design of Persistent Embedded Main Memory Databases on Non-Volatile Memory,” in 软件学报, Journal of Software, 2016, 27 (Suppl.2), pp. 320-327 (in Chinese). (EI Indexed)

14.    “Morphable Resistive Memory Optimization for Mobile Virtualization”. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 35, No. 6, pp. 891-904, Jun. 2016(SCI Indexed, JCR Q2)

15.    “A Compiler Assisted Wear Leveling for Morphable PCM in Embedded Systems,” in Journal of Systems Architecture (JSA), 2016. doi: 10.1016/j.sysarc.2016.06.007. (SCI Indexed, JCR Q2)

16.    “Write Reconstruction for Write Throughput Improvement on MLC PCM based Main Memory,” in Journal of Systems Architecture (JSA), 2016. (SCI Indexed) doi:10.1016/j.sysarc.2016.05.006(SCI Indexed, JCR Q2)

17.    “Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories,” in Journal of Signal Processing Systems (JSPS), Volume 84, Issue 1, pp 151-162, July 2016. (SCI Indexed, JCR Q4)

18.    “Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput,” in Journal of Signal Processing Systems (JSPS), Volume 84, Issue 1, pp 123-137, July 2016. (SCI Indexed, JCR Q4)

19.    “Efficient Data Placement for Improving Data Access Performance on Domain Wall Memory,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2016. (SCI Indexed, JCR Q2)

20.    A Time, Energy, and Area Efficient Domain Wall Memory based SPM for Embedded Systems,” in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2016. (SCI Indexed, JCR Q2)

21.    “Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint”, published in Journal of Signal Processing Systems (JSPS), Vol. 81, Issue 3, pp. 359-375, Dec. 2015. (SCI Indexed, JCR Q4)

22.    "Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs," published in IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 26, No. 9, pp.2549-2560, Sept. 2015 (SCI Indexed, JCR Q1)

 

(Referred Conference Papers)

23.    "On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints," IEEE International Conference on Computer Design (ICCD), Boston, MA, USA, Nov. 2017. (THE BEST PAPER AWARD)

24.    UDORN: A Design Framework of Persistent In-Memory Key-value Database for NVM”. In Proceedings of IEEE Non-volatile Memory System & Applications Symposium (NVMSA), Hsinchu, Taiwan, China, Aug. 2017.

25.    “减少多表连接对非易失性存储器写操作的研究”,in the 15th CCF Annual Conference on Embedded Systems (ESTC 2017), Shenyang, China, Nov. 2017.The Best Student Paper Award

26.    “Optimizing Data Placement of MapReduce on Ceph-Based Framework under Load-Balancing Constraint,” Proc. International Conference on Parallel and Distributed Systems (ICPADS), Wuhan, China, Dec. 2016

27.    “Performance Optimization for In-Memory File Systems on NUMA Machines,” Proc. 17th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), Guangzhou, China, Dec. 2016.

28.    “Optimal Functional Assignment and Communication Selection under Timing Constraint for Self-Timed Pipelines,” Proc. 13th International Conference of Embedded Software and System (ICESS), Chengdu, China, Aug. 2016.

29.    “The Design and Implementation of an Efficient Data Consistency Mechanism for In-Memory File Systems,” Proc. 13th International Conference of Embedded Software and System (ICESS), Chengdu, China, Aug. 2016.

30.    “The Design and Implementation of a High-Performance Hybrid Memory File System,” Proc. International Conference on Advanced Cloud and Big Data (CBD), Chengdu, China, Aug. 2016.

31.    “The Design of an Efficient Swap Mechanism for Hybrid DRAM-NVM Systems,” Proc. International Conference on Embedded Software (EMSOFT), Pittsburgh, PA, USA, Oct. 2016.

32.    “Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines,” Proc. International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Pittsburgh, PA, USA, Oct. 2016.

33.    “Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory,” Proc. 14th USENIX Conference on File and Storage Technologies (FAST 2016), Santa Clara, USA, Feb. 2016.

34.    “Designing an Efficient Persistent In-Memory File System,” Proc. the 4th IEEE Non-Volatile Memory System and Applications Symposium (NVMSA), Hongkong, Aug. 2015. (THE BEST PAPER AWARD)

35.    "Area and Performance Co-Optimization for Domain Wall Memory in Application-Specific Embedded Systems," in Proc. of the 52nd Design Automation Conference (DAC 2015), San Francisco, CA, USA, Jun. 2015, pp.20:1-20:6.

36.    "Optimizing Data Placement for Reducing Shift Operations on Domain Wall Memories," in Proc. of the 52nd Design Automation Conference (DAC 2015), San Francisco, CA, USA, Jun. 2015, pp.139:1-139:6.

37.    "Maximizing IO Performance via Conflict Reduction for Flash Memory Storage Systems," in Proc. of the 18th International Conference on Design, Automation, and Test in Europe (DATE 2015), Grenoble, France, March 2015.

38.    "nCode, Limiting Harmful Writes to Emerging Mobile NVRAM through Code Swapping, " in Proc. of the 18th International Conference on Design, Automation, and Test in Europe (DATE 2015), Grenoble, France, March 2015.

39.    "On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems," in Proc. of the 17th IEEE International Conference on High Performance Computing and Communications (HPCC/CSS/ICESS 2015), New York, USA, Aug. 2015, pp: 260-265.

 

荣誉及奖励

招生信息

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