个人资料
教育经历1996.09-2000.07 南京航空航天大学 学士 2000.09-2003.07 浙江大学 硕士 2004.09-2007.09 东京大学 博士 工作经历2003.07 - 2004.09 上海华虹NEC电子有限公司，研发工程师 2007.10 - 2010.11 东京大学，历任研究员、特任助理教授 2010.12 - 2011.02 南京大学 电子科学与工程学院，兼职教授 2011.03 - 2012.02 IBM国际半导体联盟/Globalfoundries公司，首席器件研发工程师 2012.03 - 2013.12 南京大学 电子科学与工程学院，教授/博导 2014.01 - 2022.04 浙江大学 信息与电子工程学院，教授/博导 2022.05 - 至今 华东师范大学 集成电路科学与工程学院 院长/教授 个人简介1977年生，国家万人计划/海外高层次人才计划入选者，IEEE高级会员（Senior Member），（美国）加州大学伯克利分校访问学者。2007年（日本）东京大学博士毕业和工作一段时间后，前往美国Globalfoundries公司和IBM国际半导体研发联盟从事先进集成电路器件与工艺的研发工作。2012年全职回国，先后在南京大学、浙江大学担任教授、博导。目前担任华东师范大学集成电路科学与工程学院院长。主要研究方向为：1）逻辑存储融合架构的器件与芯片（存算一体化等），2）亚10纳米（锗硅和锗基等）CMOS器件工艺、器件物理及可靠性。已多次在国际电子器件领域的权威会议IEEE International Electron Devices Meeting (IEDM)、IEEE Symposium VLSI Technology、IEEE International Reliability Physics Symposium(IRPS)上报告研究成果，获得2020年IRPS最佳论文奖(Best Paper Award),以第一作者或通讯作者发表论文逾百篇。申请专利40多项。目前负责国家科技创新2030——“新一代人工智能”重大项目，曾负责国家“973”项目课题负责人，国家“02”重大科技专项项目中7/5nm、14nm 工艺研发相关课题、国家自然科学基金面上项目和浙江省重点研发计划项目等重要科研任务，并与国内主要集成电路制造、设计和应用企业保持着深入、良好的合作关系。 社会兼职IEDM Sub-committee ESSDERC Sub-committee IRPS Sub-Committee ASICON Program Committee Co-Chair IEEE ICSICT Technical Program Committee Co-Chair 中国仿真学会第一届集成微系统建模与仿真专业委员会委员 研究方向1）逻辑存储融合架构的器件与芯片（存算一体化等） 2）亚10纳米（锗硅和锗基等）CMOS器件工艺、器件物理及可靠性 招生与培养开授课程本科生： 1. 《微电子导论》 2. 《专业实习》 硕博生： 1. 《半导体器件与芯片可靠性》 2. 《集成电路前沿研讨》 3. 《集成电路制造》 4. 《VLSI工艺技术》 科研项目承担了20余项国家及省级重要科研项目，包括科技部“科技创新-2030”重大项目，国家重大基础研究计划（“973”）课题，国家自然科学基金项目等。
学术成果著书 1. Yi Zhao（主编）. Wafer level reliability of advanced 2. Yi Zhao. Lanthanum-based oxides as high k gate dielectrics for next generation MOS devices. Semiconductor Research Trends. (第四章) Frank Columbus, Editor. Nova Science Publisher, New York (2007). ISBN: 1-60021-579-3 授权中国国内专利20余项，授权美国专利2项，授权日本专利1项。 以第一作者或通讯作者发表SCI论文或EI论文逾130篇。 [69] 8F2 Ternary Content Addressable Memory Array Utilizing Interface Passivated Ge Memory-diodes with 2 × 105 Self-rectifying Ratio, IEEE Electron Device Letters. 45(2024)833-836. [68] Optimizing interface properties of HfO2/Si0.73Ge0.27 gate stacks through sulfur passivation and post-deposition annealing, Journal of Applied Physics. 135(2024)125704. [67] Impact of Bottom Electrode Crystallinity on Ferroelectricity of La-doped HfO2, IEEE Electron Device Letters. 44(2023)1833. (封面文章) [66] Phase Transitions and Anti-Ferroelectric Behaviors in Hf1-xZrxO2 Films, IEEE Electron Device Letters. 44(2023)1780. [65] Area-efficient Integration of Embedded 0.5F0.5R Hybrid Memory and High Mobility Logic Device on Ge, IEEE Transactions on Electron Devices. 70(2023)5119. [64] Forming-Free HfOx-Based Resistive Memory With Improved Uniformity Achieved by the Thermal Annealing-Induced Self-Doping of Ge, IEEE Transactions on Electron Devices. 70(2023)1671. [63] A Highly Compact Nonvolatile Ternary Content Addressable Memory (TCAM) With Ultralow Power and 200-ps Search Operation, IEEE Transactions on Electron Devices. 69(2022)4259. [62] Fermi Level Pinning Engineering for Achieving High Performance Ge-based Resistive Memory with Ultra-High Self-Rectifying Ratio (> 105), IEEE Transactions on Electron Devices. 69(2022)6751. [61] Fast Algorithms for Exact IR Drop De-Embedding in Analog Multiply–Accumulate Computing, IEEE Transactions on Electron Devices. 69(2022)6376. [60] Re-examination of Hot Carrier Degradation Mechanism in Ultra-scaled nFinFETs, IEEE Electron Device Letters. 43(2022)1802. [59] Wake-up Free La-doped HfO2-ZrO2 Ferroelectrics Achieved with An Atomic Layer-Specific Doping Technique, IEEE Electron Device Letters. 43(2022)1665. [58] Improvement of ferroelectricity and reliability in Hf0.5Zr0.5O2 thin films with two-step oxygen vacancy engineering, IEEE Electron Device Letters. 43(2022)1057. [57] Non-Volatile Flash Memory on Ge with an Oxidation-induced Self-assembled Charge Trapping Layer, IEEE Electron Device Letters. 44(2022)842. [56] Mobility improvement in accumulation-mode GeOI pMOSFETs with back interface rearrangement by H2 annealing, Applied Physics Express. 15(2022)064005-1. [55] Systematic studies of the effects of group-III dopants (La, Y, Al, and Gd) in Hf0.5Zr0.5O2 ferroelectrics by ab initio simulations, Applied Physics Letters. 119(2021)172903. [54] Stabilization of the ferroelectric phase in Hf-based oxides by oxygen scavenging, Applied Physics Express. 14(2021)126503-1. [53] Ge-based non-volatile memories, Japanese Journal of Applied Physics. 59(2020)SM0802. [52] Direct-Bandgap Electroluminescence From Germanium With Subband Engineering Utilizing a Metal-Oxide-Semiconductor Structure, IEEE Transactions on Electron Devices. 67(2020)2016. [51] Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs, IEEE Journal of the Electron Devices Society. 8(2020)577. [50] Systematic Study of Medium States inSpin-Transfer Torque MagnetoresistanceRandom Access Memory and TheirImplication for the Bit Error Rate, IEEE Electron Device Letters. 41(2020)557. [49] An Euler-Lagrange Equation Oriented Solution for Write Energy Minimization of STT-MRAM, IEEE Transaction on Electron Devices. 66(2019)3686. [48] Ge/Oxide Structured Programmable Phototransistors, IEEE Electron Device Letters. 40(2019)632. [47] High-Source–Drain Voltage-Induced Reliability Issues of Sub-28-nm Node MOSFET’s Application in Resistive-Type Nonvolatile Memory Array, IEEE Transaction on Electron Devices. 65(2018)5199. [46] Quantitative Characterization of Fast-Trap Behaviors in Al2O3/GeOx/Ge pMOSFETs, IEEE Transaction on Electron Devices. 65(2018)2729. [45] Back Gate Modulation in UTB GeOI pMOSFETs with Advanced Substrate Fabrication Technique, IEEE Transaction on Electron Devices. 65(2018)895. [44] Ge-Based Asymmetric RRAM Enable 8F2 Content Addressable Memory, IEEE Electron Device Letters. 39(2018)1294. [43] Real-Time Polarization Switch Characterization of HfZrO 4 for Negative Capacitance Field-Effect, IEEE Electron Device Letters. 39(2018)1469. [42] A Fast Vth Measurement (FVM) Technique for NBTI Behavior Characterization, IEEE Electron Device Letters. 39(2018)172. [41] Experimental investigation of ballistic carrier transport for sub-100-nm Ge n-MOSFETs, IEEE Electron Device Letters. 38(2017)434. [40] Investigation of self-heating effect on ballistic transport characterization for Si FinFETs featuring ultrafast pulsed IV technique, IEEE Transactions on Electron Devices. 64(2017)909. [39] Strain Engineering for Germanium-on-Insulator Mobility Enhancement with Phase Change Liner Stressors, Chinese Physics Letter. 34(2017) 108101. [38] High performance Ge ultra-shallow junctions fabricated by a novel formation technique featuring spin-on dopant and laser annealing for sub-10 nm technology applications, Microelectronic Engineering. 168(2017)1-4. [37]. Electrothermal Effects on Hot-Carrier Reliability in SOI MOSFETs-AC Versus Circuit-Speed Random Stress, IEEE Transactions on Electron Devices. 63(2016)3669. [36] Demonstration of ultra-thin buried oxide germanium-on-insulator MOSFETs by direct wafer bonding and polishing techniques, Applied Physics Letters. 109(2016)023503. [35] Aggressive EOT scaling of Ge pMOSFETs with HfO2/AlOx/GeOx gate stacks fabricated by ozone post oxidation, IEEE Electron Device Letters. 37(2016)831. [34] High performance germanium pMOSFETs with NiGe metal source/drain fabricated by microwave annealing, IEEE Transactions on Electron Devices. 63(2016)2665. [33] Comparison of Different Scattering Mechanisms inthe Ge (111), (110), and (100) Inversion Layersof nMOSFETs With Si nMOSFETs UnderHigh Normal Electric Fields, IEEE Transaction on Electron Devices. 62(2015)1136. [32] Reduction of Reactive-Ion Etching-Induced Ge Surface Roughness by SF6/CF4 Cyclic Etching for Ge Fin Fabrication, Chinese Physics Letter. 32(2015) 045202. [31] High performance trench MOS barrier Schottky diode with high-k gate oxide, Chinese Physics B. 24(2015)77201. [30] Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor, Chinese Physics Letter. 32(2015) 117302. [29] Experimental Study on NBTI Degradation Behaviors in Si pMOSFETs Under Compressive and Tensile Strains, IEEE Electron Device Letters. 35(2014)714. [28] Experimental Investigation on Alloy Scattering in sSi/Si0.5Ge0.5/sSOI Quantum-Well p-MOSFET, IEEE Transaction on Electron Devices. 61(2014)950. [27] Retarded thermal oxidation of strained Si substrate, Chinese Physics B. 23(2014)066103. [26] Impact of Si cap, strain and temperature on the hole mobility of (s)Si/sSiGe/(s)SOI quantum-well p-MOSFETs, Microelectronic Engineering, 113(2014)5. [25] Comparative study on strain induced electrical properties modulation of Si p-n junctions, Applied Physics Letters. 102(2013) 093502. [24] Fabricating Au micro-pattern arrays on flexible substrate with high fidelity, Microelectronic Engineering,105 (2013)46. [23] EOT Scaling of Al2O3/Germanium(Ge) Metal-Oxide-Semiconductor Capacitors with Ozone Post Oxidation, Chinese Physics B 6(2013)067701. [22] Mechanical tensile strain induced gate and substrate currents change in n and p-channel metal-oxide-semiconductor field-effect transistors, Applied Physics Letters. 101(2012) 053507. [21] Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices, Materials, 5(2012)1413. [20] Effect of Sample Thickness on SiO2/Si Interface Roughness Characterization through Transmission Electron Microscope Measurements in Strained-Si MOSFETs, Journal of the Electrochemical Society. 159(2012)H57. [19] Suppression of interface state generation in Si MOSFETs with biaxial tensile strain, IEEE Electron Device Letters. 32(2011)1005. [18] Projection effect on extraction of Si/SiO2 interface roughness from high-resolution transmission electron microscopy measurements, Journal of Applied Physics. 109(2011)014511. [17] Projection effect on extraction of Si/SiO2 interface roughness from high-resolution transmission electron microscopy measurements, Journal of Applied Physics. 109(2011)014511. [16] A novel characterization scheme of Si/SiO2 interface roughness for surface roughness scattering-limited mobility in unstrained- and strained-Si MOSFETs, IEEE Transaction on Electron Devices.57(2010)2057. [15] Thermodynamic analysis of moisture absorption phenomena in high permittivity oxides as gate dielectrics of advanced CMOS devices. Applied Physics Letters. 96(2010)242901. [14] Comprehensive understanding of Coulomb scattering mobility in biaxially-strained Si pMOSFETs, IEEE Transaction on Electron Devices. 56(2009)1152. [13] On Surface roughness scattering mobility in biaxially-strained Si pMOSFETs, IEEE Electron Device Letters. 30(2009)987. [12] Amorphous high k LaTaOx films for alternative gate dielectrics. Journal of Applied Physics105(2009)034103. [11] Band gap enhancement and electrical properties of high-k LaYOx films for alternative gate insulators. Applied Physics Letters. 94(2009)042901. [10] Poly silicon over-etching time control of advanced [9] Moisture absorption and leakage current suppression of lanthanum oxide films as high k gate dielectric. Japan Journal of Applied Physics., 46(7A)(2007)4189. [8] Substrate and process dependence of gate oxide reliability of 0.18μm dual gate CMOS process. Acta Physica Sinica.55(2006)3003. [7] Higher-k LaYOx films with strong moisture resistance. Applied Physics Letters. 89(2006)252905. [6] Moisture- absorption-induced permittivity deterioration and surface roughness enhancement of lanthanum oxide films on silicon. Applied Physics Letters. 88(2006)072904. [5] Voltage to breakdown and charge to breakdown investigation of gate oxide of 0.18μm dual gate CMOS process with different measurement methods. Journal of Semiconductors.27(2006)290. [4] Comparison of via electromigration with self-ionized plasma and MOCVD methods for barrier metal deposition. Journal of The Electrochemical Society.105(2005)G831. [3] Unit capacitance distribution of a silicon nitride MIM capacitor in silicon wafer. Semiconductor Science and Technology.20(2005)330. [2] One method for fast gate oxide TDDB lifetime projection. Journal of Semiconductors.26(2005)2271. [1] Electromigration of a metal line with the poly silicon heating method Journal of Semiconductors.26(2005)1653. International conferences (*Corresponding Author) [67] Impact of Hot Carrier Degradation and Bias Temperature Instability on GHz Cycle-to-cycle Variation in Ultra-scaled FinFETs, IEEE International Reliability Physics Symposium (IRPS) 2024, Dallas, Texas, USA. [66] Physical Study of Low-frequency TDDB Lifetime Deterioration in Advanced FinFETs, IEEE International Reliability Physics Symposium (IRPS) 2024, Dallas, Texas, USA. [65] Orthorhombic-I Phase and Related Phase Transitions: Mechanism of Superior Endurance (>1014) of HfZrO Anti-ferroelectrics for DRAM Applications, IEEE International Reliability Physics Symposium (IRPS) 2024, Dallas, Texas, USA. [64] High Mobility SiGe/Ge Channel Transistors for Advanced CMOS Technology, China Semiconductor Technology International Conference (CSTIC)2023, Shanghai, China (邀请报告). [63] GHz Cycle-to-Cycle Variation in Ultra-scaled FinFETs: From the Time-Zero to the Aging States, IEEE International Reliability Physics Symposium (IRPS) 2023, Monterey, CA, USA. [62] Interval time dependent wake-up effect of HfZrO ferroelectric capacitor,IEEE International Reliability Physics Symposium (IRPS) 2023, Monterey, CA, USA. [61] GHz AC to DC TDDB Modeling with Defect Accumulation Efficiency Model, IEEE International Reliability Physics Symposium (IRPS) 2023, Monterey, CA, USA. [60] GHz C-V Characterization Methodology and Its Application for Understanding Polarization Behaviors in High-k Dielectric Films, IEEE International Reliability Physics Symposium (IRPS) 2022, Dallas,Texas, USA. [59] Degradation Behaviors of 22 nm FDSOI CMOS Inverter Under GHz AC Stress, IEEE International Reliability Physics Symposium (IRPS) 2022, Dallas,Texas, USA. [58] Universal Hot Carrier Degradation Model under DC and AC Stresses, IEEE International Reliability Physics Symposium (IRPS) 2022, Dallas,Texas, USA. [57]. Neural Network Acceleration and Voice Recognition with a Flash-based In-Memory Computing SoC, IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2021, Washington DC, DC, USA. [56] Current Research Status and Future Prospect of the In-Memory Computing, IEEE 14th International Conference on ASIC (ASICON) 2021, Kunming, China. [55] Combined-solvent engineering of HPbI3 for efficient FAPbI3 perovskite solar cells, IEEE 14th International Conference on ASIC (ASICON) 2021, Kunming, China. [54] Self-powered Electrochromic Windows for Smart Homes Realized by Hybridizing Enhanced Perovskite Solar Cells, IEEE 14th International Conference on ASIC (ASICON) 2021, Kunming, China. [53] Nanosecond-scale and self-heating free characterization of advanced CMOS transistors utilizing wave reflection, IEEE International Reliability Physics Symposium (IRPS) 2021. Monterey, CA, USA. [52] MRAM Acceleration Core for Vector Matrix Multiplication and XNOR-Binarized Neural Network Inference, IEEE International Symposium on VLSI Technology Systems and Applications (VLSI-TSA)2020. Hsinchu, Taiwan, China, [51] Superior Data Retention of Programmable Linear RAM (PLRAM) for Compute-in-Memory Application, IEEE International Reliability Physics Symposium (IRPS) 2020. New Jersey, USA(virtual) [50] In-Situ Monitoring of Self-Heating Effect in Aggressively Scaled FinFETs and Its Quantitative Impact on Hot Carrier Degradation Under Dynamic Circuit Operation, IEEE International Reliability Physics Symposium (IRPS) 2020.New Jersey, USA(virtual) [49] Programmable Linear RAM: A New Flash Memory based Memristor for Artificial Synapses and Its Application to Speech Recognition System, IEEE International Electron Devices Meeting(IEDM) 2019San Francisco, USA. [48] Probing Write Error Rate and Random Telegraph Noise of MgO based Magnetic Tunnel Juction Using a High Throughput Characterization System, IEEE International Reliability Physics Symposium (IRPS) 2019. San Francisco, USA. [47] Ge-based Non-Volatile Logic-Memory Hybrid Devices for NAND Memory Application, IEEE International Electron Devices Meeting (IEDM) 2018 San Francisco, USA. [46] Resistive Switching Behaviours and Novel Device Applications of Metal-Oxide-Si/Ge Structures, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2018. San Francisco, CA, USA. [45] Will Self-heating be Seriously Problematic in Sub-10nm Technology Nodes, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2018. San Francisco, CA, USA. [44] Scattering Mechanisms in Inversion Layers of Ge MOSFETs: Impact of Surface States and Carrier Effective Masses, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2018. San Francisco, CA, USA. [43] Non-Volatile Ternary Content Addressable Memory (TCAM) with Two HfO 2 /Al 2 O 3 /GeO x /Ge MOS Diodes, IEEE VLSI Technology Symposium.2018. Hawaii, USA. [42] Effect of Measurement Speed (µs-800 ps) on the Characterization of Reliability Behaviors for FDSOI nMOSFETs, IEEE International Reliability Physics Symposium 2018. San Francisco, USA. [41] Ultrafast pulse characterization of hot carrier injection effects on ballistic carrier transport for sub-100 nm MOSFETs, IEEE International Reliability Physics Symposium (IRPS) 2017. San Francisco, USA. [40] Ultra Fast (<1 ns) Electrical Characterization of Self-heating Effect and Its Impact on Hot Carrier Injection in 14nm FinFETs, IEEE International Electron Devices Meeting (IEDM) 2017. San Francisco, USA. [39] NiGe Metal Source/Drain Ge pMOSFETs for Future High Performance VLSI Circuits Applications, 12th IEEE International Conference on ASIC (ASICON) 2017. Guiyang, China. [38] A 55nm Logic Process Compatible p-Flash Memory Array Fully Demonstrated with High Reliability, 12th IEEE International Conference on ASIC (ASICON) 2017. Guiyang, China. [37] Demonstrate High ROFF/RON Ratio and Forming-Free RRAM for rFPGA Application based on Switching Layer Engineering, 12th IEEE International Conference on ASIC (ASICON) 2017. Guiyang, China. [36] Experimental study on hole and electron effective masses in inversion layers of Ge (100), (110) and (111) p- and n-MOSFETs, IEEE International Electron Devices Meeting (IEDM). 2016 San Francisco, USA. [35] High performance and reliability Ge channel CMOS with a MoS2 capping layer, IEEE International Electron Devices Meeting (IEDM). 2016 San Francisco, USA. [34] Fast-trap characterization in Ge CMOS using sub-1 ns ultra-fast measurement system, IEEE International Electron Devices Meeting (IEDM). 2016 San Francisco, USA. [33] Reliability Improvement of Ge pMOSFETs with Al2O3 Dielectric by Ozone Post Annealing, IEEE 13th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) 2016, Hangzhou, China. [32] Reduction of Junction Leakage Current in Sub-10 nm Ultra-Shallow NiGe/n-Ge Schottky Junctions by Dopant Segregation, IEEE 13th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) 2016.Hangzhou, China. [31]. Impact of Ozone Post Oxidation to the Electrical Properties of HfO2/Al2O3/GeOx/Ge pMOSFETs, International Conference on Solid State Devices and Materials (SSDM) 2016. Tsukuba, Japan. [31] On the Characterization of Hot Carrier Effect in Fully Depleted SOI and GeOI MOSFETs under Circuit-Speed Random Stress, International Conference on Solid State Devices and Materials (SSDM) 2016. Tsukuba, Japan. [30] RTN and Low Frequency Noise on Ultra-scaled Near-ballistic Ge Nanowire nMOSFETs, IEEE SYMPOSIUM ON VLSI TECHNOLOGY 2016. Honolulu, HI, USA. [28] PBTI and HCI Degradations of Ultrathin Body InGaAs-on-Insulator nMOSFETs Fabricated by Wafer Bonding, IEEE International Reliability Physics Symposium (IRPS). 2015. CA, USA. [27] Plasma Post‐Oxidation of Ultrathin ALD High‐k/Ge Structures for Advanced Gate Stacks in High Mobility Ge CMOS Devices”，The 2nd International Conference on ALD Applications & 3rd China ALD Conference 2014, Shanghai, China. [26] Comprehensive Experimental Study on Impacts of Compressive and Tensile Strains on NBTI Degradation Behaviors in Si pMOSFETs, IEEE Si Nanoelectronic Workshop (SNW). 2014 Hawaii, USA. [25] Comprehensive Experimental Study on Impacts of Compressive and Tensile Strains on NBTI Degradation Behaviors in Si pMOSFETs, IEEE International Reliability Physics Symposium (IRPS) 2014. Hawaii, USA. [24] Mobility Enhancement and Slow Traps Reduction in Interfacial Layer-Free Al2O3/Ge pMOSFETs with Ozone Post Annealing, IEEE Semiconductor Interface Specialists Conference (SISC. 2013. Arlington, VA, USA. [23] Strain-induced I-V Characteristics Modulation of p-n Junctions and MOS Capacitors in Si CMOS Devices, IEEE International Workshop on Junction Technology, (IWJT) 2013. Kyoto, Japan. (邀请报告) [22] Effect of Alloy Scattering on Hole Mobility of sSi/sSiGe/sSOI Quantum Well pMOSFETs, International Conference on Solid State Devices and Materials (SSDM) 2013. Tsukuba Japan. [21] Interface Stabilizing and EOT Scaling of Al2O3/Ge Gate Stack with Ozone Post-Oxidation without Additional Interface Layer Formation, International Conference on Solid State Devices and Materials (SSDM). 2012 Kyoto Japan. [20]. Electrical properties of strained Si p-n junctions, 11th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). 2012Xi'an, China. [19] Self-diffuse Nanostructures on Silicon Surfaces through Rapid Annealing at High Temperatures, 11th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT) 2012.Xi'an, China. [18] Mechanical strain altered gate and substrate currents in n and p-channel MOSFETs, International Meeting for Future of Electron Devices, 2012, Kansai, Japan. [17] Evidence of Correlation between Surface Roughness and Interface States Generation in Unstrained and Strained-Si MOSFETs, IEEE VLSI Technology Symposium. 2010. Hawaii, USA. [16] Comprehensive Understanding of Surface Roughness Limited Mobility in Unstrained- and Strained-Si MOSFETs by Novel Characterization Scheme of Si/SiO2 Interface Roughness, IEEE VLSI Technology Symposium2009. Kyoto, Japan. [15] Comprehensive understanding of surface roughness and Coulomb scattering mobility in biaxially-strained Si MOSFETs, IEEE International Electron Devices Meeting (IEDM). 2008 San Francisco, USA. [14] Mechanisms of and solutions to moisture absorption of lanthanum oxide as high k gate dielectric, 211th Meeting of The Electrochemical Society2007. ChicagoUSA. [13] Materials science-based device performance engineering for metal gate high-k [12] Moisture absorption and leakage current suppression of lanthanum oxide films as high k gate dielectric, International Conference on Solid State Devices and Materials (SSDM) 2006. Yokohama Japan. [11] Higher-k LaYOx films with strong moisture-robustness, 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT) 2006. Shanghai China. [10] Dielectric properties of metal-doped HfO2 for higher-k gate insulators, International Meeting for Future of Electron Devices2006. Kyoto Japan (邀请报告) [9] Dielectric properties of amorphous LaTaOx films for alternative gate dielectrics, International Workshop on Dielectric Thin Films for Future ULSI Devices: Science and Technology (IWDTF) 2006. Kanagawa Japan. [8] Moisture- absorption-induced permittivity deterioration and surface roughness enhancement of lanthanum oxide films on silicon, International Conference on Solid State Devices and Materials (SSDM) 2005. Kobe Japan [7] Moisture-absorption-induced permittivity deterioration and surface roughness enhancement of lanthanum oxide films on silicon, 1st UT-SNU-TU Student Workshop2005.Tokyo, Japan. [6] One method for fast gate oxide TDDB lifetime prediction, 39th International Symposium on Microelectronics (IMAPS)2005. Philadelphia, Pennsylvania. USA [5] Voltage to breakdown and charge to breakdown investigation of gate oxide of 0.18μm dual gate CMOS process with different measurement methods, SEMI-ECS International Semiconductor Technology Conference (ISTC) 2005. Shanghai China. [4] Comparison of via EM with self ionized plasma and MOCVD methods for barrier metal deposition, SEMI-ECS International Semiconductor Technology Conference (ISTC) 2005. Shanghai China. [3] Charge to breakdown investigation of gate oxide with different substrate in dual gate oxide CMOS process, Twenty First VLSI/ULSI Multilevel Interconnection Conference. (VMIC) 2004. Hawaii USA. [2] Effect of poly silicon over-etching time on gate oxide reliability, Twenty First VLSI/ULSI Multilevel Interconnection Conference. (VMIC)2004. Hawaii, USA. [1] Doped HfO2 for higher-k dielectrics, 208th Meeting of The Electrochemical Society2005. Los AngelesUSA. (邀请报告)
荣誉及奖励2020年度IEEE International Reliability Physics Symposium (IRPS) Best Paper Award 2018年度浙江大学优质教学二等奖 2015年度浙江大学信息与电子工程学院先进工作者 2012年度入选国家海外高层次人才计划入选者 2012年－美国国际电子电气工程师协会（IEEE）高级会员（Senior Member） |
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赵毅 |