Bingyi Ye

B.E., Wuhan University, 

Ph.D, Peking University

Zijiang Young Scholar (Researcher), East China Normal University

Wireline transceivers and key building blocks, including:

1. High-speed wireline transceiver

2. Ultra-wideband analog front-end

3. Compensation for impairments in optical communication

[1] Bingyi Ye, Tianchen Ye, Tianyuan Zhong, Zhiwen Huang, Lei Shen, Boyang Zhang, Dunshan Yu, Yandong He, Weixin Gai,  “A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS,” ISSCC 2025.

[2] Guangdong Wu*, Yuanliang Li*, Bingyi Ye*, Fangzhu Li, Xin Liu, Haowei Niu, Ruixu Wang, Dunshan Yu, Weixin Gai, “A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS,” ISSCC 2025 (*Equally Credited Authors).

[3] Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He, “A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS,” IEEE JSSC, 2024.

[4] Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu, “A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS,” IEEE JSSC, 2023.

[5] Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He, “A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS,” ISSCC, 2023.

[6] Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu, “A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS,” ISSCC, 2022.

[7] Zhifei Wang, Zhiwen Huang, Tianchen Ye, Bingyi Ye, Fangzhu Li, Wei Wang, Dunshan Yu, Weixin Gai,“A 64Gb/s/wire 10.5Tb/s/mm/layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS,” ISSCC 2025.

[8] Boyang Zhang*, Tianchen Ye*, Shuaizhe Ma, Tianyuan Zhong, Xin Liu, Fangzhu Li, Bingyi Ye, Dan Li, Weixin Gai, “A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON,” ISSCC 2025.

[9] Kai Sheng*, Haowei Niu*, Boyang Zhang*, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen, “A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS,” IEEE JSSC, 2023.

[10] Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou, “A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS,” ISSCC, 2023.

[11] Kai Sheng*, Haowei Niu*, Boyang Zhang*, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen, “A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS,” ISSCC, 2022.