邱翔

2008.09 - 2013.09 Ph.D, ECE Dept., University of California, Santa Barbara

2006.09 - 2008.07 硕士，微电子学研究所，清华大学

2002.09 - 2006.07 学士，电子工程系，清华大学

2022.09 - 至今 华东师范大学集成电路学院

2019.03 - 2022.08 上海闪易半导体有限公司

2013.10 - 2019.01 Synopsys Inc.

邱翔，华东师范大学集成电路学院专任研究员。分别于2006年和2008年在清华大学获得电子科学与技术专业学士学位和微电子专业硕士学位，于2013年在加州大学圣塔芭芭拉分校获得计算机工程专业博士学位。2013年至2019年在新思科技担任研发工程师，研发经理。2019年回国共同创立上海闪易半导体有限公司。2022年加入华东师范大学担任专任研究员。长期从事电子设计自动化，存算一体方向的研究。

- 存算一体

- 计算机体系结构

- 人工智能编译器

- 电子设计自动化

高性能边缘神经网络芯片研发及应用-基于闪存的存算一体化的研发及产业化，上海市浦江人才计划，主持

基于混合器件的神经形态计算架构及芯片研究，科技创新2030-“新一代人工智能”重大项目，参与

面向大规模卷积神经网络的存算一体多核芯片研究，上海市浦东新区科委，参与

1. L. Zhao, S. Gao, S. Zhang, X. Qiu, F. Yang, J. Li, Z. Chen, and Y. Zhao, Neural Network Acceleration and Voice Recognition with a Flash-based In-Memory Computing SoC, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-5.

2. S. Gao, Y. Cong, Z. Zhang, X. Qiu, C. Lee and Y. Zhao, Superior Data Retention of Programmable Linear RAM (PLRAM) for Compute-in-Memory Application, 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2020, pp. 1-5.

3. Shifan Gao, Jian Hu, Jun Xiao, Bo Zhang, Choonghyun Lee, Yi Zhao, Weiran Kong, Guangjun Yang, Xiang Qiu, Chun Yang, Cheng Zhang, Binhan Li, Chao Gao, Hong Jiang, Zhexian Wang, “Programmable Linear RAM: A New Flash Memory-based Memristor for Artificial Synapses and Its Application to Speech Recognition System”, 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 14.1.1-14.1.4.

4. Xiang Qiu, M. Marek-Sadowska and W. P. Maly, Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 869-878, May 2015.

5. Xiang Qiu, M. Marek-Sadowska and W. P. Maly, Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 4, pp. 495-506, April 2014.

6. Xiang Qiu, and M. Marek-Sadowka, Routing Challenges for Designs With Super High Pin Density, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 9, pp. 1357-1368, Sept. 2013.